1. Field of the Invention
This invention relates generally to any processing system requiring a two-dimensional transformation of source data, and more specifically to video bandwidth compression systems which use transform and coding techniques to minimize the number of coding symbols required to describe an image.
2. Description of Prior Art
Two-dimensional transforms are ordinarily generated either optically or through the use of a digital computer. Both methods suffer from severe limitations in many signal processing applications. A general purpose digital computer large enough to perform two-dimensional transforms in real time is heavy, expensive, and consumes an excessive amount of power for many airborne transform encoder applications. Coherent optical two-dimensional transform implementations interface poorly with electronic systems and the aircraft environment. Another approach to performing a two-dimensional transformation consists of performing a row by row one-dimensional transform with serial access hardware, storing the one-dimensional transform coefficients in place, and then performing a column by column one-dimensional transform. A block diagram of a row-then-colum transform processor is shown in FIG. 1. Basically, in performing an N by N transform, each row is divided into blocks of N pixels or resolution elements. A one-dimensional N-point transform is applied to each horizontal block and the transform coefficients are stored in the memory. Since N rows must be transformed and stored before the one-dimensional transform can be applied in the vertical direction, this intermediate memory size must be N lines. As indicated in FIG. 1, a redundant N-line memory is required so that while the transform is applied in the vertical direction the transform coefficients for the next N rows can be stored.
The primary shortcomings of this approach is that the processor architecture does not allow for a reduction in sample rate which, depending upon the resolution requirements of the system can be high. For instance, for a state of the art processor, the sample rate could be as high as 9.7 million samples/second.
Such a high speed requirement causes implementation problems in two areas. First of all, a "corner turning" operation is required in order to organize the row transformed coefficients before the transform can be applied in the vertical direction. This operation becomes difficult to implement at the higher speeds. More significant, though, is the high speed A/D converter requirement. State of the art A/D converters operating at 10 MHz and 8 bits are either large, expensive, or not readily available. When this is combined with low power requirements, the row-then-column implementation of the two-dimensional cosine transform does not become practical for most low cost airborne encoder applications.
Accordingly, it is an object of the present invention to provide a two-dimensional transform processor which is organized to accept high speed serial sampled analog input data and to output the results in a parallel fashion resulting in a data rate reduction for subsequent processing.
A further object is to accomplish two-dimensional transform processing at a fraction of the cost, size, weight and power required by other two-dimensional transform techniques.